Towards Employing Compilers for Thermal Management and Optimal Data Placement in Hybrid Cache

Towards Employing Compilers for Thermal Management and Optimal Data Placement in Hybrid Cache

The goal of the TECTONIC project is to alleviate the challenging problem of hot-spots in 3D stacked chip-multiprocessors by employing a software-hardware based combined approach. With the stagnation in process technology scaling new emerging memory technologies are investigated. Promise of better scalability with reduced static leakage makes Non-volatile memories (NVM) as the potential candidates to replace conventional SRAM. However, many of the proposed NVM technologies are sensitive to heat, that raised up the issue of reliability. Considering heat dissipation as an exclusive issue of hardware will not be the appropriate approach towards finding out the solutions, as running-application has direct impacts on on-chip thermal imbalance. Hence, TECTONIC will manage the on-chip temperature and eliminate hot-spots by leveraging application specific knowledge extracted at compile time in combination with new hardware mechanisms for distributing computational work and memory accesses for even heat distribution while maintaining high performance.