Context Switching Reconfigurable Hardware for Communication Systems

Programmable logic circuits are an alternative to processors. They typically offer parallel computing and more inputs and outputs than a processor as well as have a lower power consumption. They are programmed based on a circuit description similar to a program for a processor. The circuit description is the basis for a configuration that is written to the device which then determines the behavior of the circuit. This can be overwritten either in its entirety or only by a part of it. The latter enables a part of the circuit changing its function without a need for stopping the complete device. Experience so far shows that, although the benefit of reprogramming during development is applied, it is rarely used after a product has been shipped to the market. Part of the reason for this is the lack of tools and implementation examples. The focus of this project has been on developing architectures and tools that can contribute to dynamically changing configurations becoming more useful, as it has been for many years for processors. The project has included development of a tool, called GoAhead, to support the development of partial reconfiguration of programmable logic. It provides a framework for developing systems based on blocks of reconfigurable logic dynamically being replaceable. It offers flexibility and capabilities far beyond what other available tools offer. We have also worked on developing an example of how the tool can be used. The tool has gained significant attention in the international scientific community with a number of people using (or considering to use) it in their research and development. Layout planning is important for dynamic module replacement, and we have introduced an effective way this can be done and also integrated it with GoAhead. This tool for module placement has also been integrated with a multithreaded operating system developed at the University of Paderborn. This work is the result of a stay abroad for one of the doctoral students in the project. Another reason for reprogramming not being much used in industrial products is the inability to simulate such systems. Therefore, we have in the project worked on developing a framework for accurate modeling and simulation of systems that employs partial reprogramming of a circuit. We have also shown that the time for reconfiguration may be substantially reduced. Project researchers have also been involved in (at our institute) to arrange the largest and oldest conference in reconfigurable logic in August 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL). We have also collaborated in the ERASMUS project European Digital Virtual Design Lab (eDiViDe, 2011-2014) together with three other European partners. The goal is to develop a laboratory where students can access various real lab setup which they can connect to from anywhere through the Internet. Among the setups at UiO, we will show partial reconfiguration in practice by creating designs with our developed GoAhead tool.

Much of the focus on computer hardware is on the speed and performance of the latest processors. In parallel to this development, reconfigurable logic devices (Field Programmable Gate Arrays - FPGAs) are getting faster and contain a larger amount of confi gurable logic as well. There is a growing interest in applying the technology for computing rather than only as glue logic between processing elements. In this project, the latest of such technology will be applied for designing high performance computin g systems in embedded communication systems. Whereas hardware normally is static at run-time, software processes are being swapped at a high rate. However, in this project, architectures where the hardware configuration is dynamically changed (i.e. conte xt switching) will be investigated. Norwegian industry has shown a leading role in the design of different kinds of communication systems. Much of this has involved the design of custom hardware systems. These have often included Application Specific In tegrated Circuits (ASICs) to obtain satisfactory speed. The drawback of such systems is the lack of flexibility as frequently new protocols, features and capabilities are added. Reconfigurable technology could provide the user both increased speed by havi ng the algorithms implemented in custom hardware as well as a very flexible (like software) way of modifying the architecture. Reducing cost and power consumption have increased importance. By introducing run-time reconfigurable hardware as we would like in this project, the size of the physical hardware can be smaller than the reconfigurable logic resources otherwise required. This is since for most applications not all application functions/protocols in a system are active concurrently and by run-time reconfiguration inactive functions do not have to occupy hardware. Another benefit of run-time reconfiguration could be computational speedup.