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FORNY20-FORNY2020

Low-power Tsetlin Machine Integrated Circuits

Awarded: NOK 0.50 mill.

The Tsetlin Machine (TM) is a promising logic-based machine learning algorithm developed by Professor Ole-Christoffer Granmo at the University of Agder. The TM has been tested on many different types of datasets and has shown competitive performance compared to neural nets that are dominant in the field of artificial intelligence. Research on TM - both at the algorithm level and at the hardware level - is now taking place at many different universities around the world. TM solutions are based on logic, as opposed to neural nets that require energy-intensive arithmetic. With TM integrated circuits (chips), it is therefore possible to achieve energy-friendly solutions both within “internet of things” and in more complex machine learning systems. TM also has better properties compared to neural networks when it comes to explaining why the algorithm gives an answer. This is also due to its logical structure. In the project “Low-power Tsetlin Machine integrated circuits” a test chip has been developed. This is an accelerator, which is a circuit that can perform a demanding task for a processor. The alternative is a that the processor itself performs the task based on software instructions. The accelerator chip classifies simple images within 10 categories, e.g. it can determine handwritten numbers between 0 and 9. Several basic building blocks for TM low-energy hardware solutions have been tested with this chip. A technique has also been found that reduces switching in parts of the digital circuit modules of the TM chip. This has the potential to further reduce energy consumption, and a patent application has been filed for this technique. The measurement results from the chip are very promising and show energy efficiency better than state-of-the-art. As for the patent-pending solution, the preliminary results do not show as much power reduction as expected, but with other TM chip architectures, greater benefits can be achieved. The development of the chip and the results from the measurements will be described in a scientific article which will be submitted to a high quality journal for publication. The chip results show the excellent properties of the TM algorithm in terms of resource utilization (chip area), image classification accuracy and, not least, energy efficiency. Furthermore, the circuit is based on a classic design-flow for synchronous digital integrated circuits. The solution can therefore easily be included in larger system-on-chips. The accelerator chip represents an important milestone for low-power TM hardware.

I prosjektet er det utviklet en integrert krets (chip) basert på Tsetlin Machine (TM) algoritmen. Målinger på denne chipen viser en energieffektivitet bedre enn det som er rapportert på forskningsfronten. Vi tror og håper dette vil vise det store potensialet TM har innenfor laveffekt elektronikk, typisk for anvendelser innenfor «tingenes internett» der enheter ofte er batteriopererte og det er strenge krav til effektforbruk. Også for større og mer komplekse maskinlæringssystemer kan TM-basert elektronikk gi betydelig besparelse i energiforbruk. Kretsen og måleresultatene vil bli beskrevet i en vitenskapelig artikkel som vil bli sendt til en journal tidlig i 2025. Vi mener chipen representerer en viktig milepæl for lav-effekt TM-maskinvare og danner et godt grunnlag for videre forskning og utvikling. Det er søkt om patent på en løsning som reduserer digital svitsjeenergi for den typen TM arkitektur som er benyttet i chipen. Patentet er til behandling. Aktiviteter knyttet til mulig lisensiering og videreføring av patentet, gitt at det innvilges, er startet. Det ble ikke observert så stor gevinst i effektreduksjon som vi hadde håpet, men løsningen som er patentsøkt kan benyttes også i andre TM kretsarkitekturer der den kan gi større gevinst.

Funding scheme:

FORNY20-FORNY2020