ENIAC Call 2 ESIP Efficient Silicon Multi-Chip System-in-Package Integration

In the ESiP project we will study reliability, failures and investigate testing for high density silicon multi-chip integration. This includes the study of new reliability targets and methods, new methods of failure characterization for highly integrated systems, new failure modes, known good die (KGD) testing, test strategies and methodologies for System-in-Package. The project starts at the silicon level, but includes also the interaction of the chip/package system with the board, which will become more and more important in the future. Partners of the full value chain participate in ESiP: semiconductor suppliers, system houses, test and analytical equipment suppliers and material suppliers are involved to reach the project targets. The results achieved for reliability, failure analysis and test methods will be assessed by industrial relevant test vehicles. Integrated silicon samples will be designed that are applicable for medical or communication applications. Sensonor's contribution to the project wi ll be within definition of specifications and requirements for system reliability within their market segments automotive and security, definition of appropriate test vehicles, as well as their manufacturing. For Conpart, the project will involve developm ent and reliability assessment of conductive adhesive technology. Specifically, reliability requirement definition, test strategy development, as well as establishement of design rules and optimization of processes for chip stacking and heterogeneous inte gration will be carried out. SINTEF will function as national coordinator of the project and contribute technically within system reliability testing and test method identification and development, failure analysis, root cause identification and systemati c catalogisation of observed failure modes. The project ESiP has Infineon Technologies AG, Germany, as coordinator. 41 partners from 9 European countries participate in the project.